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| the A4408 is power management ic that uses a buck or buck-boost pre-regulator to efficiently convert automotive battery voltages into a tightly regulated intermediate voltage, complete with control, diagnostics, and protections. the output of the pre-regulator supplies a 5 v / 1 15 ma max tracking/protected ldo, a 3.3 v / 165 ma max ldo, a 5 v / 325 ma max ldo, and an adjustable output synchronous buck regulator (1.25 v typ / 700 ma dc ). designed to supply can or microprocessor power supplies in high-temperature environments, the A4408 is ideal for underhood applications. enable inputs to the A4408 include a logic-level (enb) and two high-voltage (enbat1 and enbat2) inputs. the A4408 provides flexibility by including a track pin to set the reference of the tracking regulator to either the 5 v or the 3.3 v output, so the A4408 can be adapted across multiple platforms with different sensors and supply rails. the mode pin selects the npor undervoltage threshold for the v5 and v5p outputs. diagnostic outputs from the A4408 include a power-on-reset output (npor). pok5v indicates the status of the 5 v and 5 v protected ldos. fault flag 0 (ff0) and fault flag 1 (ff1) retain the last fault to reset the microcontroller. dual bandgaps, one for regulation and one for fault checking, improve long- term reliability of the A4408. the A4408 contains a watchdog timer that can be programmed to accept a wide range of clock frequencies (wd adj ). the watchdog timer has a fixed activation delay to accommodate processor startup. the watchdog timer has an enable/disable pin (active low, wd enn ) to facilitate initial factory programming or field reflash programming. protection features include under- and overvoltage lockout on all four cpu supply rails. in case of a shorted output, all linear regulators feature foldback overcurrent protection. in addition, A4408-ds, rev. 1 ? automotive aec-q100 qualified ? 2.8 to 36 v in operating range, 40 v in maximum ? buck or buck-boost pre-regulator (vreg) ? adjustable pwm switching frequency: 250 khz to 2.4 mhz ? pwm frequency can be synchronized to external clock ? adjustable synchronous buck regulator (1.25 v nom ) ? 3.3v (3v3) and 5v (v5) internal ldo regulators with foldback short-circuit protections ? 5v (v5p) internal tracking ldo regulator with foldback short-circuit and short-to-battery protections ? track sets either 3v3 or v5 as the reference for v5p ? power -on reset (npor) with fixed delay of 15 ms ? programmable watchdog timer with activation delay ? active-low watchdog timer enable pin (wd enn ) ? dual bandgaps for increased reliability: bg vref , bg fault ? mode pin sets the npor undervoltage threshold for v5 and v5p ? fixed pok5v undervoltage threshold for v5 and v5p ? logic enable input (enb) for microprocessor control ? t wo ignition enable inputs (enbat1 and enbat2) adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 package: 38-pin etssop (suffix lv) figure 1: A4408 simplified block diagram not to scale A4408 5.35 v (vreg) buck-boost pre-regulator 3.3 v ldo (3v3) with foldback protection 1.25 v (1v25) synchronous buck regulator programmable watchdog timer with activation delay dual bandgaps charge pump ff0 / ff1, uv, hic, tsd, wd pok5v output npor output tracking control 2:1 mux 3v3 v5 ref 5 v ldo (v5p) with tracking, foldback, and short to v bat protection 5 v ldo (v5) with foldback protection continued on next page... features and benefits description applications electronic power steering (eps) t ransmission control units (tcu) advanced braking systems (abs) emissions control modules other automotive applications continued on next page... january 27, 2017
2 selection guide part number package packing [1] lead frame A4408klvtr-t 38-pin etssop with thermal pad 4000 pieces per 7-inch reel 100% matte tin 1 contact allegro for additional packing options. ? ff0, ff1 fault flagslast microcontroller reset indicators ? slew rate control pin helps reduce emi/emc ? frequency dithering helps reduce emi/emc ? overvoltage and undervoltage protection for all four cpu supply rails ? pin-to-pin and pin-to-ground tolerant at every pin ? thermal shutdown protection ? ?40c to 150c junction temperature range the v5p output is protected from a short-to-battery event. both switching regulators include pulse-by-pulse current limit, hiccup mode short-circuit protection, lx short-circuit protection, missing asynchronous diode protection (vreg), and thermal shutdown. the A4408 is supplied in a low profile (1.2 mm maximum height) 38-lead etssop package (suffix lv) with exposed thermal pad. features and benefits (continued) description (continued) absolute maximum ratings [2] characteristic symbol notes rating unit vin v vin ?0.3 to 40 v enbat1, enbat2 v enbatx with current limiting resistor [3] ?13 to 40 v ?0.3 to 8 v i enbatx 75 ma lx1, slew ?0.3 to v vin + 0.3 v t < 250 ns ?1.5 v t < 50 ns v vin + 3 v v vcp, cp1, cp2 ?0.3 to 50 v v5p v v5p independent of v vin ?1 to 40 v all other pins ?0.3 to 7 v junction temperature t j ?40 to 150 c storage temperature range t stg ?40 to 150 c 2 stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability 3 the higher enbat1 and enbat2 ratings (C13 v and 40 v) are measured at node a in the following circuit confguration: + - node ?a? 450 ven enbatx gnd A4408 thermal characteristics: may require derating at maximum conditions; see application information characteristic symbol test conditions [4] value unit junction to pad thermal resistance r jc etssop-38 (lv) package 30 c/w 4 additional thermal information available on the allegro website. specifications adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 3 table of contents features and benefits 1 description 1 applications 1 package 1 simplified block diagram 1 selection guide 2 absolute maximum ratings 2 thermal characteristics 2 functional block diagram / typical schematic 4 pinout diagram and terminal list table 6 electrical characteristics 7 buck and buck-boost pre-regulator specifications 7 adjustable synchronous buck regulator 10 linear regulator (ldo) 12 control inputs 13 diagnostic outputs 15 watchdog timer (wdt) 18 functional description 19 overview 19 buck-boost pre-regulator (vreg) 19 adjustable sync. buck regulator (1v25/adj) 20 low-dropout linear regulators (ldos) 21 tracking input (track) 21 watchdog timer (wdt) 21 dual bandgaps (bg vreg , bg fault ) 22 adjustable frequency and sync. (fset/sync) 22 frequency dithering and lx1 slew rate control 22 enable inputs (enb, enbat) 23 bias supply (v cc ) 23 charge pump (vcp, cp1, cp2) 23 startup and shutdown sequences 23 fault reporting (npor, mode, pok5v) 24 fault flags (ff0, ff1) 24 startup and shutdown logic table 25 summary of fault mode operation table 26 t iming diagrams 28 design and component selection 37 pwm switching frequency (r fset ) 37 charge pump capacitors 37 pre-regulator ouput inductor (l1) 37 pre-regulator output capacitance 37 pre-regulator ceramic input capacitance 38 pre-regulator asynchronous diode (d1) 38 pre-regulator boost mosfet (q1) 38 pre-regulator boost diode (d2) 38 pre-regulator soft-start and hiccup timing (c ss1 ) 38 pre-regulator compensation (r z1 , c z1 , c p1 ) 39 synchronous buck component selection 40 setting the output voltage (r fb1 and r fb2 ) 40 synchronous buck output inductor (l2) 40 synchronous buck output capacitance 40 synchronous buck compensation (r z2 , c z2 , c p2 ) 41 synchronous buck soft-start and hiccup timing 41 linear regulators 42 internal bias (v cc ) 42 signal pins (npor, pok5v, ff0, ff1) 42 rc snubber calculations (r snubx , c snubx ) 43 pcb layout recommendations 45 package outline drawing 53 adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 4 2 4. 7 f 50 v 1210 0. 1 f 0603 vbat key_sw bg vref ldos on A4408 vin vin foldback v5 2. 2 f 5v ldo 3v3 2.2 f 3.3v ldo foldback sync (optional) vcc ss1 comp1 0.47 f bg vref 75 m? vreg 5 10 f 16 v/ x7 r/ 1206 (38 C 4 3 f @ 5.3v ) buck-boost pre-regulator (vreg) (w/ hiccup mode) fb lx1 lx1 lg 2k comp1 and ss1 reset vcp uv vreg on stop pwm vss1 rst vss2 rst ss_o k mpor master ic por ( mpor) * indicates a latched fault 3.3v typ 2.6v typ clk 1mhz osc2 watchdog timer wd fault one shot 2m s typ wd osc wd adj r adj 64.9 k for 2 0m s wd clk wd in clk in wd enn = 0 or open enables wd 60 k wd enn wd enn wd start clk 1mhz enbat2 3.3v typ 2.6v typ 650 k enbat1 650 k enb 60 k gnd gnd tsd fset/sync ref v5 3v 3 2:1 mux 01 select track startup / shutdown sequence fb adj o n ldos on vreg on r fset 8.66 k 100 f 50 v/ 250 m din ss3p 4 d1 ss3p4 d2 ss3p 4 l1 6.8 h, 5 0m ihlp2525czer6r8m01 v5p foldback 5v tracking ldo short to vbat protection 2.2 f adjustable synchronous buck regulator (1.2 5v typ ) (w/ hiccup mode) clk @ f osc lx2 pgnd pgnd lx2 comp2 ss2 1v25/fbadj bg vref comp2 & ss2 reset c ss2 10 nf r z2 6.81 k? c z2 1. 5n f c p2 47 pf 3 10 ?f 16 v/x7r/1206 (27 C 30 ?f @ 1.2 5v ) l2 4.7? h, 9 5m ? ihlp1616bzer4r7m11 1.25 v 700m a 1a peak su/sd 0.1? f 50 v d3 bas16j d4 mss1p5 cp helper circuit. these components required if v vin < 6v. wd adj,fault vcp charge pump vcp uv/ov 1. 0? f i enbat1(bias) i enbat2(bias) ib track i slew clk @ f osc fset uv/ov osc1 cp2 cp1 0.22 ?f c ss1 22 nf r z1 22.1 k c z1 1. 5n f c p1 100 pf c vcc 1 f d5 mss1p5 vreg en ldo 3. 6v bg1_uv bg1 bg vref bg2 bg fault bg2_uv v in(start) v in(stop) v in(uvlo) vcc microcontroller enable 0.22 f * * for negative v_ign or v_acc transient suppression v_ig n 3. 3k 7.5k 7. 5v mmsz 4693t1 0.22 f * v_acc 3.3k 7. 5k 7.5v mmsz 4693t1 q1 : nvtfs4823n or sqs420en or stl10n3llh5 v5 325 ma max 3v3 165m a max v5 p 115m a max 20 k npor vcc pok5v 20 k vcc ov/uv detect & delays 1v25/ fbadj 3.3v npor de- glitch t dfilt wd start wd fault wd adj,fault pok5v bg fault de- glitch t dfilt v5 v5p ff1 last reset state (latched) on/off rst clk 1mhz clear latches ss_o k mode ib mode uv,l1 or uv,l2 uv detect pok, l su/s d npor set 20 k v5 (or vcc) ff0 20 k v5+v5p+3v3+fb adj +vcp uv wd fault hic vreg +hic 1v25 +tsd de- glitch td filt falling delay t dldo(off) on/off su/sd vcc uv, vcp uv bg1_uv, bg2_uv *vcp ov, *d1 missing *slew uv/ov *i lim,lx1 , *ov > t dov v in(uvlo) v5 u v fb adj u v 3v3 uv mpor v5p uv fb adj on i 1v25/fbadj lxb lx 1l x2 0603 50 v 0603 50 v 0603 50 v 1206 1/ 4w 0603 1/10 w 0603 1/10 w snubbers reduce ringing and high-frequency noise/emissions lxb slew r slew 22.1 k 2.49 k [1] figure 2: functional block diagram/typical schematic buck-boost mode (f osc = 2 mhz) 1 for optimal no-load operation. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 5 comp1 lx1 lx1 lg vreg cp1 cp2 c p1 27 pf r z1 13.3 k c z1 2.7 nf these components required if v< 6 v vin d3 bas16j d4 mss1p5 0.1 f 50 v l1 4.7 h, 37 m ihlp2525czer4r7m01 310 f 16 v/x7r/1206 (23? 26 f @ 5.3 v) d1 ss2p4 5.35 v typ 0.47 f A4408 figure 3: functional block diagram modifcations for buck only mode, f osc = 2 mhz f sw = 500 khz f sw = 2 mhz ambient temperature (c) percent of maximum load power derating at v vin = 3 to 36 v 120% 100% 80% 60% 40% 20% 10% -40 -20 0 20 40 60 80 100 120 140 160 figure 4: thermal derating for buck-boost operation down to 3 v adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 6 terminal list table number name function 1 vcp charge pump reservoir capacitor 2, 3 vin input voltage 4, 9 gnd ground 5 mode sets uv threshold for v5/v5p in npor logic. mode pin does not affect pok5v threshold. gnd/lowCnpor uv is set high at v v5x(uv,l1) . open/ highCnpor uv is set low at v v5x(uv,l2) . 6 vcc internal voltage regulator bypass capacitor pin 7 ss1 soft-start programming pin for buck-boost pre-regulator 8 comp1 error amplifier compensation network pin for buck-boost pre-regulator 10 track tracking control: open/high C v5p tracks 3v3, gnd/low C v5p tracks v5 11 npor active-low, open-drain regulator fault detection output 12 pok5v power ok output indicating when either v5 or v5p rail is undervoltage (uv). pok5v uv threshold is always at v v5x(pok,l) . 13, 14 ff0, ff1 open-drain, latched fault flag (ffx) outputs indicate last type of fault to reset microcontroller. ff0 and ff1 bits are only valid if npor has first transitioned high. ff0 and ff1 latches are reset when all A4408 enable inputs are low and soft-start voltages have decayed below reset thresholds. see table 2 for more details. 15 fset/ sync frequency setting and synchronization input 16 enbat1 ignition enable input from key/switch via 1 k of resistance 17 enbat2 ignition enable input from key/switch via 1 k of resistance 18 enb logic enable input from microcontroller 19 3v3 3.3 v regulator output 20 wdin watchdog refresh input (rising edge triggered) from microcontroller or dsp 21 wdadj watchdog wait/delay time is programmed by connecting r adj from this pin to ground 22 wdenn watchdog enable pin: open/low C wd is enabled, high C wd is disabled 23 v5p 5 v tracking/protected regulator output 24 ss2 soft-start programming pin for adjustable synchronous buck regulator 25 1v25/ fbadj feedback pin for 1.25 v (or adjustable) synchronous buck regulator 26 comp2 error amplifier compensation network pin for 1.25 v synchronous regulator 27, 28 pgnd power ground for adjustable synchronous regulator and its gate driver 29, 30 lx2 switching node for adjustable synchronous buck regulator 31 v5 5 v regulator output 32 vreg output of buck-boost and input for ldos and adjustable synchronous buck regulator 33 lg boost gate drive output for buck-boost pre-regulator 34 slew slew rate adjustment for rise time of lx1 35, 36 lx1 switching node for buck-boost pre-regulator 37, 38 cp1, cp2 charge pump capacitor connections C pad exposed thermal pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 pa d vcp vin vin gnd mode vcc ss1 comp1 gnd track npor pok5v ff0 ff1 fset/sync enbat1 enbat2 enb 3v3 cp2 cp1 lx1 lx1 slew lg vreg v5 lx2 lx2 pgnd pgnd comp2 1v25/fb adj ss2 v5p wd enn wd adj wd in package lv, 38-pin etssop pinout diagram adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 7 characteristic symbol test conditions min. typ. max. unit general specifications operating input voltage v vin after v vin > v vin(start) , and v enb > 2 v or v enbatx > 3.5 v, buck-boost mode 2.8 13.5 36 v after v vin > v vin(start) , and v enb > 2 v or v enbatx > 3.5 v, buck mode 5.7 13.5 36 v vin uvlo st art voltage v vin(start) v vin rising 5.1 5.4 5.7 v vin uvlo stop voltage v vin(stop) v vin falling 2.53 2.64 2.78 v vin uvlo hysteresis v vin(hys) v vin(start) ? v vin(stop) C 2.7 C v supply quiescent current [1] i q v vin = 13.5 v, v enbatx 3.6 v or v enb 2 v, v vreg = 5.6 v (no pwm) C 13 C ma i q(sleep) v vin = 13.5 v, v enbatx 2.2 v and v enb 0.8 v C C 10 a pwm switching frequency and dithering oscillator frequency f osc r fset = 8.66 k? 1.8 2.0 2.2 mhz r fset = 19.1 k? [3] C 1.0 C mhz r fset = 52.3 k? [3] 343 400 457 khz pwm switching frequency foldback thresholds f sw v vreg > 2.7 v, v vin rising, f osc f osc /2 18.7 19.5 20.3 v v reg > 2.7 v, v vin falling, f osc /2 f osc C 18.5 C v v reg > 2.7 v, v vin rising, f osc /2 f osc C 7.5 C v v reg > 2.7 v, v vin falling, f osc f osc /2 6.7 7.0 7.4 v frequency dithering f osc as a percent of f osc C 12 C % dither/slew start threshold v in(ds,on) 8.5 9.0 9.5 v dither/slew stop threshold v in(ds,off) 7.8 8.3 8.8 v vin dithering/slew hysteresis v in(ds,hys) C 700 C mv charge pump (vcp) output voltage v vcp v vcp C v vin , v vin = 13.5 v, v vreg = 5.5 v, i vcp = 6.5 ma, v comp1 = v comp2 = 0 v, v enb = 3.3 v 4.1 6.6 C v v vcp C v vin , v vin = 6.5 v, v vreg = 5.5 v, i vcp = 6.5 ma, v comp1 = v comp2 = 0 v, v enb = 3.3 v 3.6 4.4 C v switching frequency f sw(cp) C 65 C khz vcc pin voltage output voltage v vcc v vreg = 5.35 v C 4.65 C v thermal protection thermal shutdown threshold [3] t tsd t j rising 155 170 185 c thermal shutdown hysteresis [3] t hys C 20 C c 1 for input and output current specifcations, negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. electrical characteristics C buck and buck-boost pre-regulator [1] : valid at 3.6 v [2] < v vin < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. continued on next page... adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 8 characteristic symbol test conditions min. typ. max. unit output voltage specifications buck output voltage C regulating v vreg v vin = 13.5 v, enb = 1, 0.1 a < i vreg < 1.25 a 5.25 5.35 5.45 v pulse-width modulation (pwm) pwm ramp offset v pwm1offs v comp1 for 0% duty cycle C 400 C mv lx1 rising slew rate control [3] lx1 rise v vin = 13.5 v, 10% to 90%, i vreg = 1 a, r slew = 22.1 k C 0.9 C v/ns v vin = 13.5 v, 10% to 90%, i vreg = 1 a, r slew = 150 k C 0.3 C v/ns lx1 falling slew rate [3] lx1 fall v vin = 13.5 v, 90% to 10%, i vreg = 1 a C 1.5 C v/ns buck minimum on-time t on(min,buck) C 85 160 ns buck maximum duty cycle d max(buck) C 100 C % boost duty cycle (lg pin) d min(bst) [3] after v vin > v vin(start) , v vin = 6.5 v C 20 C % d max(bst) after v vin > v vin(start) , v vin = 3.5 v 53 61 66 % comp1 to lx1 current gain gm power1 C 4.5 C a/v slope compensation [3] s e1 f osc = 2 mhz 1.04 1.48 1.92 a/s f osc = 400 khz 0.22 0.33 0.44 a/s internal mosfet mosfet on-resistance r dson v vin = 13.5 v, t j = ?40c [3] , i ds = 0.1 a C 50 65 m? v vin = 13.5 v, t j = 25c [4] , i ds = 0.1 a C 75 90 m? v vin = 13.5 v, t j = 150c, i ds = 0.1 a C 150 180 m? mosfet leakage i fet(lkg) v enbatx 2.2 v and v enb 0.8 v, v lx1 = 0 v, v vin = 16 v, ?40c < t j < 85c [4] C C 10 a v enbatx 2.2 v and v enb 0.8 v, v lx1 = 0 v, v vin = 16 v, ?40c < t j < 150c C 50 150 a error amplifier open-loop voltage gain [3] a vol1 C 60 C db transconductance gm ea1 v ss1 = 750 mv 550 750 950 a/v v ss1 = 500 mv 275 375 500 a/v output current i ea1 C 75 C a maximum output voltage v ea1(vo,max) 1.3 1.7 2.1 v minimum output voltage v ea1(vo,min) C C 300 mv comp1 pull-down resistance r comp1 hiccup1 = 1 or fault1 = 1 or v enbatx 2.2 v and v enb 0.8 v, latched until v ss1 < v ss1(rst) C 1 C k? 1 for input and output current specifcations, negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. 4 specifcations at 25c or 85c are guaranteed by design and characterization, not production tested. electrical characteristics C buck and buck-boost pre-regulator (continued) [1] : valid at 3.6 v [2] < v vin < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. continued on next page... adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 9 characteristic symbol test conditions min. typ. max. unit boost mosfet (lg) gate driver lg high output voltage v lg(on) v vin = 6 v, v vreg = 5.35 v 4.6 C 5.5 v lg low output voltage v lg(off) v vin = 13.5 v, v vreg = 5.35 v C 0.2 0.4 v lg source current 1 i lg(on) v vin = 6 v, v vreg = 5.35 v, v lg = 1 v C ?300 C ma lg sink current 1 i lg(off) v vin = 13.5 v, v vreg = 5.35 v, v lg = 1 v C 150 C ma soft-start ss1 offset voltage v ss1(offs) v ss1 rising due to i ss1(su) C 400 C mv ss1 fault/hiccup reset voltage v ss1(rst) v ss1 falling due to hiccup1 = 1 or fault1 = 1 or v enbatx 2.2 v and v enb 0.8 v 140 200 275 mv ss1 startup (source) current i ss1(su) v ss1 = 1 v, hiccup1 = fault1 = 0 ?10 ?20 ?30 a ss1 hiccup (sink) current i ss1(hic) v ss1 = 0.5 v, hiccup1 = 1 5 10 15 a ss1 delay time t ss1(dly) c ss1 = 22 nf C 440 C s ss1 ramp time t ss1 c ss1 = 22 nf C 880 C s ss1 pull-down resistance r pd(ss1) fault1 = 1 or ic disabled, latched until v ss1 < v ss1(rst) C 3 C k? ss1 pwm frequency foldback f sw1(ss) 0 v < v vreg < 1.3 v typ , v comp1 = v ea1vo(max) C f osc /8 C C 0 v < v vreg < 1.3 v typ , v comp1 < v ea1vo(max) C f osc /4 C C 1.3 v typ < v vreg < 2.7 v typ C f osc /2 C C v vreg > 2.7 v typ C f osc C C hiccup mode hiccup1 ocp pwm counts t hic1(ocp) v ss1 > v hic1(en) , v vreg < 1.3 v typ , v comp = v ea1vo(max) C 30 C pwm cycles v ss1 > v hic1(en) , v vreg > 1.3 v typ , v comp = v ea1vo(max) C 120 C pwm cycles current protections pulse-by-pulse current limit i lim1(ton,min) v vin < 7.0 v, t on = t on(min) 4.1 4.6 5.1 a v vin > 7.0 v, t on = t on(min) 2.5 2.8 3.3 a lx1 short-circuit current limit i lim(lx1) latched fault 6.0 7.0 C a missing asynchronous diode (d1) protection detection level v d(open) ?1.9 ?1.5 ?1.0 v time filtering [3] t d(open) 50 C 250 ns 1 for input and output current specifcations, negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. electrical characteristics C buck and buck-boost pre-regulator (continued) [1] : valid at 3.6v < v vin < 36 v [2] , C40c < t a = t j < 150c, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 10 characteristic symbol test conditions min. typ. max. unit feedback reference voltage feedback voltage accuracy v 1v25/fbadj 50 ma < i 1v25 < 700 ma 1.23 1.25 1.27 v pulse-width modula tion (pwm) pwm ramp offset v pwm2(offs) v comp2 for 0% duty cycle ? 350 ? mv high-side mosfet minimum on-time t on(min) ? 65 105 ns high-side mosfet minimum off-time t off(min) does not include total gate driver non-overlap time, t no ? 100 125 ns gate driver non-overlap time [3] t no ? 15 ? ns comp2 to lx2 current gain gm power2 ? 3.7 ? a/v slope compensation [3] s e2 f osc = 2 mhz 0.45 0.63 0.81 a/s f osc = 400 khz 0.12 0.14 0.19 a/s internal mosfets high-side mosfet on-resistance r dson(hs) t a = 25c [4] , i ds = 100 ma ? 200 235 m i ds = 100 ma ? ? 400 m lx2 node rise/fall time [3] t r/f(lx2) v vreg = 5.5 v ? 12 ? ns high-side mosfet leakage [2] i dss(hs) v enbatx 2.2 v and v enb 0.8 v, v lx2 = 0 v, v vreg = 5.5 v, ?40?c < t j < 85?c [4] ? ? 2 a v enbatx 2.2 v and v enb 0.8 v, v lx2 = 0 v, v vreg = 5.5 v, ?40c < t j < 150c ? 3 15 a low-side mosfet on-resistance r dson(ls) t a = 25c [4] , i ds = 100 ma ? 55 65 m i ds = 100 ma ? ? 110 m low-side mosfet leakage [2] i dss (ls) v enbatx 2.2 v and v enb 0.8 v, v lx2 = 5.5 v, ?40?c < t j < 85?c [4] ? ? 1 a v enbatx 2.2 v and v enb 0.8 v, v lx2 = 5.5 v, ?40c 11 characteristic symbol test conditions min. typ. max. unit soft-start ss2 offset voltage v ss2(offs) v ss2 rising due to i ss2(su) 120 200 270 mv ss2 fault/hiccup reset voltage v ss2(rst) v ss2 falling due to hiccup2 = 1 or fault2 = 1 or v enbatx 2.2 v and v enb 0.8 v ? 100 120 mv ss2 startup (source) current i ss2(su) v ss2 = 1 v, hiccup2 = fault2 = 0 ?10 ?20 ?30 a ss2 hiccup (sink) current i ss2(hic) v ss2 = 0.5 v, hiccup2 = 1 5 10 20 a ss2 to v 1v25 delay time t ss2(dly) c ss2 = 10 nf C 100 C s v 1v25 ramp time t ss2 c ss2 = 10 nf C 600 C s ss2 pull-down resistance r pd(ss2) fault2 = 1 or v enbatx 2.2 v and v enb 0.8 v, latched until v ss2 < v ss2(rst) C 2 C k? ss2 pwm frequency foldback f sw2(ss) v 1v25/fbadj < 450 mv typ C f osc /4 C C 450 mv typ < v 1v25/fbadj < 780 mv typ C f osc /2 C C v 1v25/fbadj > 780 mv typ C f osc C C hiccup mode hiccup2 ocp enable threshold v hic2(en) v ss2 rising C 2.3 C v hiccup2 ocp counts t hic2(ocp) v ss2 > v hic2(en) , v 1v25/fbadj < 450 mv typ C 30 C pwm cycles v ss2 > v hic2(en) , v 1v25/fbadj > 450 mv typ C 120 C pwm cycles current protections high-side mosfet pulse-by-pulse current limit i lim2(5%) duty cycle = 5% 1.8 2.1 2.7 a low-side mosfet reverse current limit i lim2(ls) C 500 C ma 1 for input and output current specifcations, negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. 4 specifcations at 25c or 85c are guaranteed by design and characterization, not production tested. electrical characteristics C adjustable synchronous buck regulator [1] (continued): valid at 3.6 v [2] < v vin < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 12 characteristic symbol test conditions min. typ. max. unit v5 and v5p linear regulators v5 accuracy and load regulation v v5 10 ma < i v5 < 325 ma, v vreg = 5.25 v 4.9 5.0 5.1 v v5 output capacitance [3] c out(v5) 1.0 C 22 f v5p accuracy and load regulation v v5p 10 ma < i v5p < 115 ma, v vreg = 5.25 v 4.9 5.0 5.1 v v5p output capacitance [3] c out(v5p) 1.5 2.2 4.1 f v5 and v5p minimum output voltage, buck only mode [3] v v5x(min1) (5.5 v bat ) v vcp = 8.60 v, track = 1, i v5 = 265 ma, i v5p = 35 ma, i 3v3 = 75 ma, i 1v25 = 250 ma 1) t a = 150c, v vin = 5.26 v, v vreg = 5.14 v 2) t a = ?40c [3] , v vin = 5.04 v, v vreg = 4.97 v 4.82 C C v v v5x(min2) (4.5 v bat ) v vcp = 7.70 v, track = 1, i v5 = 265 ma, i v5p = 35 ma, i 3v3 = 75 ma, i 1v25 = 250 ma 1) t a = 150c, v vin = 4.26 v, v vreg = 4.14 v 2) t a = ?40c [3] , v vin = 4.04 v, v vreg = 3.97 v 3.65 C C v v5 and v5p minimum output voltage, buck-boost mode [3][4] v v5x(min3) v vin = 2.8 v, v vreg = 5.25 v, v vcp 7.5 v, track = 1, i v5 = 310 ma, i v5p = 110 ma, i 3v3 = 100 ma, i 1v25 = 500 ma 4.82 4.90 C v v5p tracking v5p/3v3 tracking ratio v v5p v 3v3 1.508 1.515 1.523 C v5p/3v3 tracking accuracy track 3v3 3 v < v 3v3 < 3.3 v, track = 1, i 3v3 = i v5p = 75 ma ?0.5 C +0.5 % v5p/v5 tracking accuracy track v5 3.5 v < v v5 < 5.0 v, track = 0, i v5p = i v5 = 75 ma ?25 C +25 mv v5p overcurrent protection v5p current limit [1] i lim(v5p) v v5p = 5 v ?210 ?285 C ma v5p foldback current [1] i fbk(v5p) v v5p = 0 v ?30 ?60 ?90 ma v5 overcurrent protection v5 current limit [1] i lim(v5) v v5 = 5 v ?420 ?500 C ma v5 foldback current [1] i fbk(v5) v v5 = 0 v ?40 ?75 ?180 ma v5p and v5 startup timing v5p startup time [3] t su(v5p) c v5p 2.9 f, load = 45 ? 5% (110 ma) C 175 565 s v5 startup time [3] t su(v5) c v5 2.9 f, load = 16 ? 5% (310 ma) C 150 530 s 1 for input and output current specifcations, negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. 4 see b/b schematic, cp helper circuit required when v vin < 6 v. electrical characteristics C v5 and v5p linear regulator (ldo) [1] : valid at 3.6 v [2] < v vin < 36 v, ?40c < t a = t j < 150c, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 13 electrical characteristics C 3v3 ldo and control inputs [1] : valid at 3.6 v [2] < v vin < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. characteristic symbol test conditions min. typ. max. unit 3v3 linear regulators 3v3 accuracy and load regulation v 3v3 10 ma < i 3v3 < 165 ma, v vreg = 5.25 v 3.23 3.30 3.37 v 3v3 output capacitance [3] c out(3v3) 1.0 C 22 f 3v3 minimum output voltage, buck only mode [3] v 3v3(min1) (5.5 v bat ) v vcp = 8.80 v, track = 1, i v5 = 265 ma, i v5p = 35 ma, i 3v3 = 75 ma, i 1v25 = 250 ma 1) t a = 150c, v vin = 5.26 v, v vreg = 5.14 v 2) t a = ?40c [3] , v vin = 5.04 v, v vreg = 4.97 v 3.23 3.30 C v v 3v3(min2) (4.5 v bat ) v vcp = 6.80 v, track = 1, i v5 = 265 ma, i v5p = 35 ma, i 3v3 = 75 ma, i 1v25 = 250 ma 1) t a = 150c, v vin = 4.26 v, v vreg = 4.14 v 2) t a = ?40c [3] , v vin = 4.04 v, v vreg = 3.97 v 3.20 C C v 3v3 overcurrent protection 3v3 current limit [1] i lim(3v3) v 3v3 = 3.3 v ?185 ?260 C ma 3v3 foldback current [1] i fbk(3v3) v 3v3 = 0 v ?15 ?40 ?65 ma 3v3 startup timing 3v3 startup time [3] t su(3v3) c 3v3 2.9 f, load = 33 ? 5% (100 ma) C 170 550 s ignition enable (enbat1 and enbat2) inputs enbat1, enbat2 thresholds v enbatx(h) v enbatx rising 2.9 3.3 3.5 v v enbatx(l) v enbatx falling 2.2 2.6 2.9 v enbat1, enbat2 hysteresis v enbatx(hys) v enbatx(h) C v enbatx(l) C 700 C mv enbat1, enbat2 bias current [2] i enbatx(bias) t j = 25c [4] , v enbatx = 3.51 v C 28 45 a t j = 150c, v enbatx = 3.51 v C 35 55 a enba t1, enbat2 resistance r enbatx v enbatx < 1.2 v C 650 C k logic enable (enb) input enb thresholds v enb(h) v enb rising C C 2.0 v v enb(l) v enb falling 0.8 C C v enb bias current [1] i enb(in) v enb = 3.3 v C C 175 a enb resistance r enb v enb = 0.8 v C 60 C k enb/enba tx filter/deglitch enable filter/deglitch time t den(filt) 10 15 20 s enb/enbatx shutdown delay ldo shutdown delay t dldo(off) measure t dldo(off) from the falling edge of enb and enbat1 and enbat2 to time when all ldos begin to decay 15 50 100 s 1 for input and output current specifcations, negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. 4 specifcations at 25c or 85c are guaranteed by design and characterization, not production tested. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 14 electrical characteristics C 3v3 ldo and control inputs [1] (continued): valid at 3.6 v [2] < v vin < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. characteristic symbol test conditions min. typ. max. unit track and mode inputs track and mode thresholds v th, v mh v track or v mode rising C C 2.0 v v tl, v ml v track or v mode falling 0.8 C C v track and mode bias current [1] i btrack, i bmode C C50 C a fset/sync input fset/sync pin voltage v fset/sync no external sync signal C 800 C mv fset/sync open circuit (undercurrent) detection time t fset/sync(uc) pwm switching disabled upon detection C 3 C s fset/sync short circuit (overcurrent) detection time t fset/sync(oc) pwm switching disabled upon detection C 3 C s sync. minimum frequency f sync(min) 250 C C khz sync. high threshold v sync(ih) v sync rising C C 2.0 v sync. low threshold v sync(il) v sync falling 0.5 C C v sync. input duty cycle dc sync C C 80 % sync. input pulse width t wsync 200 C C ns sync. input transition times [3] t tsync C 10 15 ns slew input slew pin operating voltage v slew C 800 C mv slew open circuit (undercurrent) detection time t slew(uc) pwm latched off if open C 3 C s slew short circuit (overcurrent) detection time t slew(oc) pwm latched off if shorted C 3 C s slew bias current [1] i slew C ?100 C na 1 for input and output current specifcations, negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. 4 specifcations at 25c or 85c are guaranteed by design and characterization, not production tested. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 15 characteristic symbol test conditions min. typ. max. unit npor ov/uv protection thresholds v5 ov thresholds v v5(ov,h) v v5 rising 5.15 5.33 5.50 v v v5(ov,l) v v5 falling C 5.30 C v v5 ov hysteresis v v5(ov,hys) v v5(ov,h) C v v5(ov,l) 15 30 50 mv v5 uv thresholds v v5(uv,h) v v5 rising, independent of the mode pin C 4.68 C v v v5(uv,l1) v v5 falling, v mode = 0 v or gnd 4.50 4.65 4.80 v v v5(uv,l2) v v5 falling, v mode = 5 v or open 3.00 3.13 3.27 v v5p output disconnect threshold v v5p(disc) v v5p rising C 7.2 C v v5p ov thresholds v v5p(ov,h) v v5p rising 5.15 5.35 5.50 v v v5p(ov,l) v v5p falling C 5.29 C v v5p ov hysteresis v v5p(ov,hys) v v5p(ov,h) C v v5p(ov,l) 45 60 75 mv v5p uv thresholds v v5p(uv,h) v v5 rising, independent of the mode pin C 4.68 C v v vp5(uv,l1) v v5p falling, v mode = 0 v or gnd 4.50 4.65 4.80 v v v5p(uv,l2) v v5p falling, v mode = 5 v or open 3.00 3.13 3.27 v 3v3 ov thresholds v 3v3(ov,h) v 3v3 rising 3.41 3.52 3.60 v v 3v3(ov,l) v 3v3 falling C 3.48 C v 3v3 ov hysteresis v 3v3(ov,hys) v 3v3(ov,h) C v 3v3(ov,l) 25 35 50 mv 3v3 uv thresholds v 3v3(uv,h) v 3v3 rising C 3.12 C v v 3v3(uv,l) v 3v3 falling 2.97 3.07 3.17 v 3v3 uv hysteresis v 3v3(uv,hys) v 3v3(uv,h) C v 3v3(uv,l) 40 50 60 mv 1v25/fbadj ov thresholds v 1v25(ov,h) v 1v25/fbadj rising 1.29 1.32 1.35 v v 1v25(ov,l) v 1v25/fbadj falling C 1.30 C v 1v25/fbadj ov hysteresis v 3v3(ov,hys) v 1v25(ov,h) C v 1v25(ov,l) 15 22 30 mv 1v25/fbadj uv thresholds v 1v25(uv,h) v 1v25 rising, triggers ldos on C 1.20 C v v 1v25(uv,l) v 1v25 falling 1.15 1.18 1.21 v 1v25/fbadj uv hysteresis v 1v25(uv,hys) v 1v25(uv,h) C v 1v25(uv,l) 10 17 25 mv 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. electrical characteristics C diagnostic outputs [1] : valid at 3.6 v [2] < v in < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. continued on next page... adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 16 characteristic symbol test conditions min. typ. max. unit npor ov delay time (first silicon will shut down if an ov is detected) overvoltage detection delay t dov v5p, v5, 3v3, and 1v25/fbadj over voltage detection delay time 6.40 8.00 9.60 ms npor turn-on and turn-off delays npor turn-on delay t dnpor(on) 12 15 18 ms npor turn-off propagation delay t dnpor(off) enb and enbat1 and enbat2 low to npor low C 15 23 s npor output voltages npor output low voltage v npor(l) enb or enbat1 or enbat2 high, v vin 2.5 v, i npor = 4 ma C 150 400 mv enb or enba t1 or enbat2 high, v vin = 1.5 v, i npor = 2 ma C C 800 mv npor leakage current [1] i npor(lkg) v npor = 3.3 v C C 2 a npor and pok5v uv filtering/deglitch uv filter/deglitch times t dfilt applies to undervoltage of 3v3, 1v25/fbadj, v5, and v5p voltages 10 15 20 s pok5v uv protection thresholds v5 and v5p rising thresholds v v5x(pok,h) v v5 or v v5p rising, independent of the mode pin C 4.68 C v v5 and v5p falling thresholds v v5x(pok,l) v v5 or v v5p falling, independent of the mode pin 4.50 4.65 4.80 v pok5v output voltages pok5v output voltage v pok5v(l) enb = 1 or enbat1 = 1 or enbat2 = 1, v vin 2.5 v, i pok5v = 4 ma C 150 400 mv enb = 1 or enba t1 = 1, enbat2 = 1, v vin = 1.5 v, i pok5v = 2 ma C C 800 mv pok5v leakage current i pok5v(lkg) v pok5v = 3.3 v C C 2 a 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. electrical characteristics C diagnostic outputs (continued) [1] : valid at 3.6 v [2] < v in < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. continued on next page... adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 17 characteristic symbol test conditions min. typ. max. unit vreg, vcp, and bg thresholds vreg ov thresholds v vreg(ov,h) v vreg rising, lx1 pwm disabled 5.50 5.65 5.90 v v vreg(ov,l) v vreg falling, lx1 pwm enabled C 5.55 C v vreg ov hysteresis v reg(ov,hys) v vreg(ov,h) C v vreg(ov,l) C 100 C mv vreg uv thresholds v vreg(uv,h) v vreg rising, triggers rise of ss2 4.14 4.38 4.62 v v vreg(uv,l) v vreg falling C 4.28 C v vreg uv hysteresis v vreg(uv,hys) v vreg(uv,h) C v vreg(uv,l) C 100 C mv vcp ov thresholds v vcp(ov,h) v vcp rising, latches all regulators off 11.0 12.5 14.0 v vcp uv thresholds v vcp(uv,h) v vcp rising, pwm enabled C 3.2 C v v vcp(uv,l) v vcp falling, pwm disabled C 2.8 C v vcp uv hysteresis v vcp(uv,hys) v vcp(uv,h) C v vcp(uv,l) C 400 C mv bgref and bgfault uv thresholds [3] v bgx(uv) v bgvref or v bgfault rising 1.00 1.05 1.10 v last microcontroller (or dsp) reset state indicators (ff0 and ff1) ff0, ff1 uv detection delay t dffx(uv) npor due to uv to ff0/ff1 latching 0.8 1.0 1.2 ms ff0, ff1 output voltage v ffx(lo) i ffx = 4 ma C C 400 mv ff0, ff1 leakage current [1] i ffx v ffx = 3.3 v C C 1 a 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. 3 ensured by design and characterization, not production tested. electrical characteristics C diagnostic outputs (continued) [1] : valid at 3.6 v [2] < v in < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 18 characteristic symbol test conditions min. typ. max. unit wd enable \ input (wd enn ) wd enn voltage thresholds v wdenn(lo) v wdenn falling, wdt enabled 0.8 C C v v wdenn(hi) v wdenn rising, wdt disabled C C 2.0 v wd enn input resistance r wd(enn) C 60 C k wd in voltage thresholds and current wd in input voltage thresholds v wdin(lo) v wdin falling, wd adj pulled low by r adj 0.8 C C v v wdin(hi) v wdin rising, wd adj charging C C 2.0 v wd in input current [1] i wdin v wdin = 5 v ?10 1 10 a wd in timing specifications wd in duty cycle d wdin 20 50 80 % watchdog activation delay t dwd(start) default 120 140 160 ms metal option 24 30 36 ms wd programming (wd adj ) wd timeout, slow clock t wd(to,slow) r adj = 32.4 k? 8.0 10 12 ms r adj = 324 k? 80 100 120 ms wd one-shot time wd pulse time after wd fault t wd(fault) 1.6 2.0 2.4 ms 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 the lowest operating voltage is only valid if the conditions v vin > v vin(start) and v vcp C v vin > v cp(uv,h) and v vreg > v vreg(uv,h) are satisfed before v vin is reduced. electrical characteristics C watchdog timer (wdt) [1] : valid at 3.6 v [2] < v vin < 36 v, C40c < t a = t j < 150c, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 19 functional description overview the A4408 is a power management ic designed for automotive applications. it contains a pre-regulator plus four dc post- regulators to create the voltages necessary for typical automotive applications such as electrical power steering and automatic transmission control. the pre-regulator can be configured as a buck or buck-boost regulator. buck-boost is required for applications that must work at extremely low battery voltages. this pre-regulator generates a fixed 5.35 v and can deliver up to 1 a to power the internal or external post-regulators. these post-regulators generate the various voltage levels for the end system. the A4408 includes four internal post-regulators: three linear regulators and one adjustable output synchronous buck regulator. the synchronous buck regulator was designed to deliver 1.25 v / 700 ma but will produce higher voltages if a feedback resistor divider is used. buck-boost pre-regulator (vreg) the pre-regulator incorporates an internal high-side buck switch and a boost switch gate driver. an external freewheeling schottky diode and an lc filter are required to complete the buck con- verter. by adding a mosfet and a schottky diode, the boost configuration can maintain all outputs with input voltages as low as 2.8 v . the A4408 includes a compensation pin (comp1) and a soft-start pin (ss1) for the pre-regulator. the A4408 can maintain its outputs over a wide range of input voltages and slew rates. actual boost performance is shown in figure 5 and figure 6 with voltages swinging between 2.9 and 18 v, and v vin slew rates ranging from 0.3 to 100v/ms. the buck-boost pre-regulator provides protection and diagnostic functions. 1. overvoltage protection 2. high voltage rating for load dump 3. switch-node-to-ground short-circuit protection 4. open freewheeling diode protection 5. pulse-by-pulse current limit 6. hiccup short circuit protection C lab measurement shown in figure 7 and detailed timing diagram shown in figure 5 figure 5: A4408 buck-boost operation at full load v vin slew rates ranging from 0.3 v/ms to 1.6 v/ms t ypical of an automotive start/stop waveform v vin(typ) = 12 v, v vin(min) = 2.9 v, 10 ms/div ch1=vin, ch2=vreg, ch3=v5 , ch4=3v3, m1=1v25, m2=v5p figure 6: A4408 buck-boost operation at full load v vin slew rates of 100 v/ms ? v5p deviates less than 0.2% v vin(typ) = 12 v, v vin(min) = 4 v, v vin(max) = 18 v ch1=vin , ch2=vreg, ch3=v5 , ch4=v5p , 500 s/div adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 20 figure 7: pre-regulator hiccup mode operation when vreg is shorted to gnd and c ss1 = 22 nf ch1=vreg, ch2=comp1 , ch3=ss1, ch4=il1, 1 ms/div for the pre-regulator, hiccup mode is enabled when pwm switching begins. if v vreg is less than 1.3 v, the number of overcurrent pulses (ocp) is limited to only 30. if v vreg is greater than 1.3 v, the number of ocp pulses is increased to 120 to accommodate the possibility of starting into a relatively high output capacitance. adjustable synchronous buck regulator (1v25/adj) the A4408 integrates the high-side and low-side mosfets necessary for implementing an adjustable output synchro- nous buck regulator. the synchronous buck is optimized for 1.25 v out / 700 ma dc / 1 a peak but can produce higher output voltages if a feedback resistor divider is inserted between vout and the 1v25/fbadj pin. the synchronous bucks pulse-by-pulse current limit depends on duty cycle and switching frequency, as shown in figure 8. an internal current sense amplifier sources 80 to 100 a to the lx2 pin. at no load, this current will slowly charge the output capacitors and raise the output voltage. therefore, the system must always sink at least 100 a, or a pull-down resistor (<2.49 k) should be used as shown in the applications schematic. protection and safety functions provided by the synchronous buck are: 1. undervoltage detection 2. overvoltage detection 3. switch-node-to-ground short-circuit protection 4. pulse-by-pulse current limit 5. hiccup short-circuit protection; lab measurement shown in figure 9 and detailed timing diagram shown in figure 23 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 ilim (a) duty cycle (%) max_2mhz typ_2mhz min_2mhz max_400khz typ_400khz min_400khz figure 8: synchronous buck pulse-by-pulse current limit the synchronous buck is powered by the 5.35 v pre-regulator output. an external lc filter is required to complete the synchro- nous buck regulator. the A4408 includes a compensation pin (comp2) and a soft-start pin (ss2) for the synchronous buck. figure 9: synchronous buck hiccup mode operation when 1v25 is shorted to gnd and c ss2 = 10 nf ch1=1v25 , ch2=comp2, ch3=ss2, ch4=il2, 500 s/div for the synchronous buck, hiccup mode is enabled when v ss2 = v hic2(en) (1.2 v typ ). if v fbadj is less than 450 mv typ , the number of overcurrent pulses (ocp) is limited to only 30. if v fbadj is greater than 450 mv typ , the number of ocp pulses is increased to 120 to accommodate the possibility of starting into a relatively high output capacitance. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 21 low-dropout linear regulators (ldos) the A4408 has three low-dropout linear regulators (ldos), one 3.3 v / 165 ma max (3v3), one 5 v / 325 ma max (v5), and one high-voltage protected 5 v / 1 15 ma max (v5p). the switching pre-regulator efficiently regulates the battery voltage to an inter- mediate value to power the ldos. this pre-regulator topology reduces ldo power dissipation and junction temperature. all linear regulators provide the following protection features: 1. undervoltage and overvoltage detection 2. current limit (ilim) with foldback short-circuit protection (ifbk); see figure 10 the protected 5 v regulator (v5p) includes protection against accidental short-circuit to the battery voltage. this makes this output most suitable for powering remote sensors or circuitry via a wiring harness where short-to-battery is possible. 100% ifbk min ifbk typ ilim min ilim typ ix vx figure 10: typical ldo foldback characteristics tracking input (track) the v5p ldo is a tracking regulator. it can be set to use either v5 or 3v3 as its reference by setting the track input pin to a logic low or high. if the track input is left unconnected, an internal current source will set the track pin to a logic high. vreg ib track sel v5 3v3 reference 5v tracking ldo v5p 2:1 mux track 0 1 figure 11: the v5p reference is set by the track input. watchdog timer (wdt) the A4408 watchdog timer monitors the time between rising edges of a clock (i.e. the clock period) applied to the wd in pin. this clock should be generated by the primary microcontroller or dsp. a watchdog fault will occur if the time between rising edges is longer than the time set by the resistor (r adj ) at the watchdog programming pin (wd adj ). a watchdog fault will pulse npor low for t wd(fault) (typically 2 ms). the watchdog circuitry is shown in figure 12. wd adj wd in wd enn wd start r adj wd clk clk in wd enn wd fa ult wd osc window wa tchdog ti mer figure 12: watchdog timer block diagram the watchdog time is programmable via the wd adj pin accord- ing to the following equation: r adj = 3.240 t wd(to,slow) where t wd(to,slow) is the longest expected clock period (in ms) and r adj is the external resistor value (in k?) needed from the wd adj pin to ground. a detailed watchdog timing diagram is shown in figure 24. the watchdog is enabled when two conditions are met: 1. the wd enn pin is a logic low, and 2. all the regulators (1v25/fbadj, 3v3, v5, and v5p) have been above their undervoltage thresholds for the watchdog start delay time, t dwd(start) (140 ms typ ). adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 22 the watchdog start delay allows the microcontroller or dsp to complete its initialization routines before delivering a clock to the wd in pin. a timing diagram documenting t dwd(start) is shown in figure 25. after regulator startup, if the wd in clock is missing (i.e. stuck low or stuck high) for at least t dwd(start) + t wd(to,slow) the A4408 will set npor, reset its counters, and repeat the watchdog startup delay. npor will periodically pulse low as long as no wdin clock is applied. a timing diagram for the missing clock situation is shown in figure 25. dual bandgaps (bg vref , bg fault ) dual bandgaps, or references, are implemented within the A4408. one bandgap (bg vref ) is dedicated solely to closed-loop control of the output voltages. the second bandgap (bg fault ) is employed for fault monitoring functions. having redundant bandgaps improves reliability of the A4408. if the reference bandgap is out of specification (bg vref ), then the output voltages will be out of specification and the monitor- ing bandgap will report a fault condition by setting npor and/or pok5v low. if the monitoring bandgap is out of specification (bg fault ), then the outputs will remain in regulation, but the monitoring circuits will report a fault condition by setting npor and/or pok5v low. the reference and monitoring bandgap circuits include two smaller secondary bandgaps that are used to detect undervoltage of the main bandgaps during power-up. adjustable frequency and synchronization (fset/sync) the pwm switching frequency of the A4408 is adjustable from 250 khz to 2.4 mhz. connecting a resistor from the fset/ sync pin to ground sets the switching frequency. an fset resistor with 1% tolerance is recommended. the fset resistor can be calculated using the following equation: r = fset f osc 21,693 () ? 2.215 where r fset is in k and f osc is the desired oscillator (pwm) frequency in khz. a graph of switching frequency versus fset resistor values is shown in figure 13. the pwm frequency of the A4408 may be increased or decreased by applying a clock to the fset/sync pin. the clock must sat- isfy the voltage thresholds and timing requirements shown in the electrical characteristics table. 0. 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 1. 8 2. 0 2. 2 2. 4 51 01 5202 53 035404 55 0556 06 57 0758 0859 0 pwm switching frequency (mhz ) r fset (k ) pwm swit ching frequency vs r fs et figure 13: switching frequency vs. fset resistor values frequency dithering and lx1 slew rate control the A4408 includes two innovative techniques to help reduce emi/emc for demanding automotive applications. first, the A4408 performs pseudo-random dithering of the pwm frequency. dithering the pwm frequency spreads the energy above and below the base frequency set by r fset . a typical fixed- frequency pwm regulator will create distinct spikes of energy at f osc , and at higher frequency multiples of f osc . conversely, the A4408 spreads the spectrum around f osc , thus creating a lower magnitude at any comparable frequency. frequency dither- ing is disabled if sync is used or v vin drops below approxi- mately 8.3 v. second, the A4408 includes a pin to adjust the rising slew rate of the lx1 pin by simply changing the value of the resistor from the slew pin to ground. slower rise times of lx1 reduce ringing and high-frequency harmonics of the regulator. the rise time may be adjusted to be relatively long and will increase thermal dissi- pation of the pre-regulator if set too high. typical lx1 slew rates are shown in table 1. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 23 table 1: typical lx1 rising slew rate vs. r slew ; lx1 snubber 8.66 / 330 pf r slew (k) lx1 rising slew rate (v/ns) lx1 10%-90% transition time at 12 v vin (ns) 8.66 1.06 9.1 22.1 0.90 10.7 46.4 0.79 12.1 71.5 0.65 14.8 100 0.50 19.2 121 0.38 25.2 150 0.29 33.1 enable inputs (enb, enbat) two enable pins are available on the A4408. a logic high on either of these pins enables the A4408. one enable (enb) is logic-level compatible for microcontroller or dsp control. the other input (enbat) must be connected to the high-voltage ignition (ign) or accessory (acc) switch through a relatively low-value series resistance, 2 to 3.6 k. for transient suppres - sion, it is strongly recommended that a 0.22 to 0.47 f capacitor be placed after the series resistance to form a low-pass filter to the enbat pin as shown in the applications schematic. bias supply (v cc ) the bias supply (v cc ) is generated by an internal linear regulator. this supply is the first rail to start up. most of the internal control circuitry is powered by this supply. the bias supply includes some unique features to ensure reliable operation of the A4408. these features include: 1. input voltage (v vin ) undervoltage lockout 2. undervoltage detection 3. short-to-ground protection 4. operation from either v vin or v vreg , whichever is higher charge pump (vcp, cp1, cp2) a charge pump provides the voltage necessary to drive the high- side n-channel mosfets in the pre-regulator and the linear regulators. two external capacitors are required for charge pump opera- tion. during the first half of the charge pump cycle, the flying capacitor between pins cp1 and cp2 is charged from either v vin or v vreg , whichever is highest. during the second half of the charge pump cycle, the voltage on the flying capacitor charges the vcp capacitor. for most conditions, the v vcp minus v vin voltage is regulated to approximately 6.5 v. the charge pump can provide enough current to operate the pre-regulator and the ldos at 2.2 mhz (full load) and 125c ambient, provided v vin is greater than 6 v . optional components d3, d4, and cp3 (refer to figure 14) must be included if v vin drops below 6 v . diode d3 should be a silicon diode rated for at least 200 ma / 50 v with less than 50 a of leakage current when v r = 13 v and t a = 125c. diode d4 should be a 1 a schottky diode with a very low forward voltage (v f ) rated to withstand at least 30 v. required if vreg is fully loaded and v< 6.0 v vin d3 bas16j d4 mss1p5 cp3 0.1 f/50 v lx1 lx1 lg cp1 cp2 cp2 0.22 f figure 14: charge pump enhancement components d3, d4, and cp3 are required if v vin < 6 v. the char ge pump incorporates some protection features: 1. undervoltage lockout of pwm switching 2. overvoltage latched shutdown of the A4408 startup and shutdown sequences the startup and shutdown sequences of the A4408 are fixed. if no faults exist and enbat or enb transition high, the A4408 will perform its startup routine. if enbat and enb are low for at least t den(filt) + t dldo(off) (typically 65 s), the A4408 will enter a shutdown sequence. the startup and shutdown sequences are summarized in table 3 and shown in timing diagrams in fig- ure 18 and figure 19. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 24 fault reporting (npor, mode, pok5v) the A4408 includes two open-drain outputs to report regulator status. the npor circuit monitors all regulator outputs for under- and overvoltage (1v25/fbadj, 3v3, v5, v5p), the watchdog timer output (wd fault ), and the thermal monitor (tsd). the pok5v circuit monitors the v5 and v5p output for undervoltage. the npor and pok5v block diagrams are shown in figure 15. the mode input pin modifies the npor circuit to raise or lower the 5 v undervoltage thresholds. if the mode pin is low, the undervoltage thresholds are relatively high, at v v5(uv,l1) . if the mode pin is high, the undervoltage thresholds are set much lower, at v v5(uv,l2) . the mode pin does not influence the pok5v cir - cuit. the pok5v undervoltage threshold is always at v v5(pok,l) . the mode input is shown in figure 15. timing diagrams of the mode pin functionality is shown in figure 16 and figure 17. there is a delay from the time all regulator voltages have risen above their undervoltage thresholds to the rising edge of npor, t dnpor(on) . this delay allows the microcontroller or dsp plenty of time to fully power-up and complete its initialization routines. the npor circuit also incorporates a delay, t dov , between the instant any regulator output exceeds its overvoltage threshold and when npor transitions low. there is minimal npor delay if any fault, other than overvoltage, occurs that requires npor to transition low. there are no significant delays in the pok5v output after v5 or v5p have risen above or fallen below their undervoltage thresh - olds. timing diagram in this datasheet shows the functionality of npor and pok5v. ov/uv detect & delays 1v25 / fbadj 3.3v npor de- glitch t dfilt wd start wd fault wd adj(fault) pok5 v bg fault de- glitch t dfilt v5 v5p mode ib mode uv,l1 or uv,l2 uv detect pok,l tsd figure 15: fault reporting circuit the v5p monitor is unique: if v5p is accidently connected to the battery voltage, then npor will bypass the normal overvoltage delay and set itself low immediately. timing diagrams showing overvoltage possibilities for v5p are shown in figure 21. the fault modes and their effects on npor and pok5v are cov- ered in detail in table 4. fault flags (ff0, ff1) the A4408 also includes two open-drain fault flags: ff0 and ff1. if a fault condition occurs and npor transitions low, ff0 and ff1 will be latched into one of three states to retain the type of fault: undervoltage of any regulator or charge pump (including v5p disconnect), hiccup mode (or tsd), or watchdog fault. a fourth state indicates no-fault. fault flag functionality is sum- marized in table 2 and shown in most timing diagrams in this datasheet. ff0 and ff1 are only valid if npor has first transitioned high. this means the A4408 must successfully complete the startup sequence and npor transitions high. the ff0 and ff1 latches are reset when all enable inputs are low and the soft-start capacitor voltages (ss1, ss2) have decayed below their reset thresholds. table 2: ff0 and ff1 fault flag status conditions ff0 ff1 type of fault detected when npor ? low low undervoltage (synchronous buck, 3v3, v5, v5p, or vcp), or v v5p > v v5p(disc) low hi-z vreg or synchronous buck in hiccup mode, or thermal shutdown (tsd) hi-z low watchdog timer (wdt) fault hi-z hi-z no fault, default condition both vreg and the synchronous buck do not enter hiccup mode for a specific number of pwm cycles. therefore, when setting ff0 and ff1, precedence is given to detecting a hiccup condi- tion (i.e. an undervoltage will occur before hiccup mode is set). to accomplish this, the undervoltage detection is delayed by t dffx(uv) . adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 25 table 3: startup and shutdown logic (signal names consistent with functional block diagram) A4408 status signals regulator control bits (0 = off, 1 = on) A4408 mode en mpor vss 1/2 low vreg uv 1v25 uv 3ldo uv vreg on 1v25 on ldos on x 1 x x x x 0 0 0 reset 0 0 1 1 1 1 0 0 0 off 1 0 0 1 1 1 1 0 0 startup 1 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 run 0 0 0 0 0 0 1 1 1 t den(filt) + t dldo(off) 0 0 0 0 0 0 1 1 0 shutdown 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 pause 0 0 1 1 1 1 0 0 0 off x = dont care en = enbat1 + enbat2 + enb vss 1/2 low = vss1 < v ss1(rst) v ss2 < v ss2(rst) 3ldo uv = 3v3_uv + v5_uv + v5p_uv mpor = v vin(uvlo) + vcc_uv + vcp_uv + bg1_uv + bg2_uv + fset_uv/ov + tsd + slew_uv/ov (latched) + vcp_ov (latched) + d1missing (latched) + i lim(lx1) (latched) + ov > t dov (latched) adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 26 table 4: summary of fault mode operation fault type and condition A4408 response to fault npor pok5v v5 snr / v5 can /v5p latched fault? reset method v5p short to vbat npor and pok5v transition low soon after v5p disconnect occurs. low when v5p sense decays low when v5p sense decays no check for short circuits on v5p v5, v5p, 3v3, or synchronous buck overvoltage if the ov condition persists for more than t dov , then set npor low and turn off all regulators. immediately set low after tdov low only if v5 or v5p are too low yes check for short circuits then cycle en or vin v5 or v5p undervoltage closed-loop control will try to raise the voltage, but may be constrained by the foldback current limit. low low no remove the short circuit or decrease the load 3v3 or synchronous buck undervoltage closed-loop control will try to raise the voltage, but may be constrained by the foldback or pulse-by- pulse current limit low not affected no remove the short circuit or decrease the load v5 or v5p overcurrent foldback current limit will reduce the output voltage. low if v5 or v5p are too low low if v5 or v5p are too low no remove the short circuit or decrease the load 3v3 overcurrent foldback current limit will reduce the output voltage. low if v 3v3 < v 3v3(uv,l) not affected no remove the short circuit or decrease the load 1v25/fbadj pin open circuit (synchronous buck output set to 1.25 v, i.e. no fb divider) the 1v25/fbadj pin will be pulled high by an internal current source; comp2 will respond by going low; lx2 will operate at zero cycle; and the synchronous buck output 0 v. low high no repair the open circuit, check the 1v25 circuitry synchronous buck output shorted to ground, v ss2 < v hic2(en) , v 1v25 < 450 mv continues to pwm, but turns of f lx2 when the high- side mosfet current exceeds i lim2 . low not affected no remove the short circuit synchronous buck overcurrent v ss2 > v hic2(en) , v 1v25/fbadj < 450 mv enters hiccup mode after 30 ocp faults. low not affected no decrease the load synchronous buck overcurrent v ss2 > v hic2(en) , v 1v25/fbadj > 450 mv enters hiccup mode after 120 ocp faults. low if v 1v25/fbadj < v 1v25(uv,l) not affected no decrease the load vreg pin open circuit v vreg will decay to 0 v; lx1 will switch at maximum duty cycle so the voltage on the output capacitors will be very close to v vin . low if 3v3, 1v25/ fbadj, v5, or v5p are too low low if v5 or v5p are too low no connect the vreg pin vreg overcurrent v vreg < 1.3 v, v comp1 = v ea1(vo,max) enters hiccup mode after 30 ocp faults. low low no decrease the load vreg overcurrent v vreg > 1.3 v, v comp1 = v ea1(vo,max) enters hiccup mode after 120 ocp faults. low if 3v3, 1v25/ fbadj, v5, or v5p are too low low if v5 or v5p are too low no decrease the load vreg overvoltage v vreg > v reg(ov,h) temporarily stop pwm switching of lx1. high high no none vreg asynchronous diode (d1) missing results in an mpor after 1 detection, so all regulators are shut off. low if 3v3, 1v25/ fbadj, v5, or v5p are too low low if v5 or v5p are too low yes populate d1 then cycle en or vin continued on next page... adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 27 fault type and condition A4408 response to fault npor pok5v v5 snr / v5 can /v5p latched fault? reset method asynchronous diode (d1) short-circuited or lx1 shorted to ground results in an mpor after 2 detections of the high- side mosfet current exceeding i lim(lx1) , so all regulators are off. low if 3v3, 1v25/ fbadj, v5, or v5p are too low low if v5 or v5p are too low yes remove the short, then cycle en or vin slew pin open circuit (slew_ov) results in an mpor, so all regulators are off. low low yes connect slew pin then cycle en or vin slew pin shorted to ground (slew_uv) results in an mpor, so all regulators are off. low low yes remove the short, then cycle en or vin fset/sync pin shorted to ground or open circuit lx1 operates at a default oscillator frequency of 1 mhz; vreg achieves 5.35 v; boost function is disabled; synchronous buck and ldos remain disabled. low low no remove short circuit, connect the pin, or populate rfset charge pump (vcp) overvoltage results in an mpor, so all regulators are off. low low yes check vcp/cp1/ cp2, then cycle en or vin charge pump (vcp) undervoltage results in an mpor, so all regulators are off. low low no check vcp/cp1/ cp2 vcp pin open circuit results in vcp_uv and an mpor, so all regulators are off. low low no connect the vcp pin or populate c cp vcp pin shorted to sround results in high current from the charge pump and (intentional) fusing of an internal trace. also results in mpor, so all regulators are off. low low no remove the short circuit and replace the A4408 cp1 or cp2 pin open circuit results in vcp_uv and an mpor, so all regulators are off. low low no connect the cp1 or cp2 pins cp1 pin shorted to ground results in vcp_uv and an mpor, so all regulators are off. low low no remove the short circuit cp2 pin shorted to ground results in high current from the charge pump and (intentional) fusing of an internal trace. also results in mpor so all regulators are off. low low no remove the short circuit and replace the A4408 bg vref or bg fault undervoltage results in an mpor, so all regulators are off. low low no raise vin or wait for bgs to power up bg vref or bg fault overvoltage if bg vref is too high, all regulators will appear to be ov (because bg fault is good). if bg fault is too high, all regulators will appear to be uv (because bg vref is good). low low no replace the A4408 vcc undervoltage or shorted to ground results in an mpor, so all regulators are off. low low no raise vin or remove short from vcc pin wd adj pin shorted to ground or open circuit a wd adj fault sets the npor output low. the remainder of the A4408 operates normally. low high no remove the short circuit or connect the pin thermal shutdown results in an mpor, so all regulators are off. low low no let the A4408 cool table 4: summary of fault mode operation (continued) adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 28 t dfilt + t dnpor(on) t dwd(start) vin (pin) v5 v5p npor wd start pok5v 12 v v v5p < v v5p(pok,l) or v v5 < v v5(pok,l) v vin(stop) t dfilt ~5 v ~4 v v v5(pok,l) v v5p(pok,l) t dfilt v v5(uv,l1) v v5p(uv,l1) t dfilt v v5p < v v5p(uv,l1) or v v5 < v v5(uv,l1) v v5p > v v5p(pok,h) and v v5 > v v5(pok,h) v v5p > v v5p(uv,h) and v v5 > v v5(uv,h) ff0 ff1 npor latches ff0 and ff1 after t dffx(uv) grey, lined areas indicate hi-z t dffx(uv) npor forces wd start low figure 16 : low vin operation with mode = low, and enb or enbat high timing diagrams (not to scale) adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 29 figure 17 : low vin operation with mode = high, and enb or enbat high 12 v v v5(uv,l2) v vin(stop) t dfilt ~5 v ~4 v v v5(pok,l) v v5p(uv,l2) v v5p(pok,l) t dfilt v v5p < v v5p(pok,l) or v v5 < v v5(pok,l) v v5p > v v5p(pok,h) and v v5 > v v5(pok,h) v5 v5 p npor wd start pok5v ff0 ff1 vin (pin ) grey, lined areas indicate hi-z adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 30 t < t dfilt t dfilt t dfilt t < t den(filt) t ss2 lx1 1v25 3v3 v5 v5p npor wd start pok5v ss1 comp1 f osc vreg 5.35 v lx2 ss2 v ss2(offs) comp2 f osc v vreg(uv,h) v 1v25(uv,h) v v5(uv,h) v v5p(pok,h) v v5p(uv,h) v v5p(pok,h) v 3v3(uv,h) t ss1 t dss1 t dss2 npor forces wd start low v 3v3(uv,l) v 3v3 < v 3v3(uv,l) and v v5p < v v5p(uv,lx) and v v5 < v v5(uv,lx) v 1v25(uv,l) 1v25,3 v3 ,v 5p ,v 5 are all uv v ss1(offs) en v v5p > v v5p(pok,h) and v v5 > v v5(pok,h) t dldo(off) shutdown sequence must finish before restart is acknowledged v pwm1(offs) v pwm2(offs) ff0 ff1 v v5p < v v5p(pok,l) or v v5 < v v5(pok,l) en forces npor low f osc / 8 / 4 / 2 f osc / 4 / 2 clear ff0/ff1 v ss1(rst) v ss2(rst) en=0, vss1 rst =1, vss2 rst =1 v v5p > v v5p(uv,h) and v v5 > v v5(uv,h) and v 3v3 > v 3v3(uv,h) and v 1v25 > v 1v25(uv,h) t dwd(start) t dnpor(off) t dfilt + t dnpor(on) t < t dfilt indicates hi-z state v v5(uv,lx) v v5p(pok,l) v v5p(uv,lx) v v5p(pok,l) f osc f osc t den(filt) f osc enb and enbat1 and enbat2 = 1 enb or enbat1 or enbat2 = 0 figure 18: startup and shutdown due to en while v vin = 12 v dc adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 31 en t dfilt t dfilt t ss2 lx1 vin 1v25 3v3 v5 v5 p npor wd start pok5v ss1 comp1 f osc vreg lx2 ss2 v ss2(offs) comp2 f osc 12 v v vreg(uv,h) v 1v25(uv,h) t ss1 t dss1 t dss2 v ss1(offs) ~5.45v @ 25c f osc f osc discharged by rpd ss1 discharged by rpd ss2 v ss2 < v ss2(rst) v vin < v vin(stop) v pwm2(offs) v pwm1(offs) v vin(start) f osc / 4 f osc / 2 f osc / 8 f osc / 4 f osc / 2 ff0 ff1 v v5p(uv,h) v v5p(pok,h) v v5(uv,h) v v5(pok,h) v 3v3(uv,h) v v5p > v v5p(pok,h) and v v5 > v v5(pok,h) v v5p < v v5p(pok,l) or v v5 < v v5(pok,l) v v5p < v v5p(uv,lx) or v v5 < v v5(uv,lx) or v 3v3 < v v3v(uv,lx) or v 1v25 < v 1v25(uv,lx) clear ff0/ff1 v v5(uv,lx) v v5(pok,l) v 3v3(uv,l) t dffx(uv) t dfilt 100% duty cycle v ss1 < v ss1(rst) and v ss2 < v ss2(rst) v v5p > v v5p(uv,h) and v v5 > v v5(uv,h) and v 3v3 > v 3v3(uv,h) and v 1v25 > v 1v25(uv,h) npor forces wd start low t dfilt + t dnpor(on) v vin > v vin(start) t dwd(start) en=0, vss1 rst =1, vss2 rst =1 enb or enbat1 or enbat2 = 1e nb and enbat1 and enbat2 = 0 figure 19: startup and dropout/shutdown due to v vin while en = 1 adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 32 a latched fault can be reset by en low if: v ss1 < v ss1(rst) and v ss2 < v ss2(rst) t dfilt t dfilt t < t dfilt t < t dfilt lx1 1v25 3v3 v5 v5 p npor wd start pok5v ss1 comp1 f osc vreg lx2 ss2 v ss2(offs) comp2 f osc v vreg(ov,h) v 1v25(uv,l) v v5p(uv,h) v v5(uv,h) v 3v3(ov,h) npor forces wd start low v 3v3(uv,h) v 1v25(uv,h) v ss1(offs) en any ov with t > t dov forces npor low v vreg(ov,l) f osc f osc v v5p > v v5p(uv,h) and v v5 > v v5 (uv,h) and v 3v3 > v 3v3(uv,h) and v 1v25 > v 1v25(uv,h) f osc v ss1(rst) v ss2(rst) t < t dfilt t < t dfilt t > t dov v pwm1(offs) v pwm2(offs) v v5p > v v5p(pok,h) and v v5 > v v5(pok,h) v v5p < v v5p(pok,l) or v v5 < v v5(pok,l) ov of vreg does not shutdown the A4408, it temporarily suspends lx1 switching t dfilt or t dnpor(on) t < t dov t < t dov t < t dov t < t dov ff0 ff1 t dwd(start) v v5(pok,l) v3v3 ov is shown, identical cases if: v v5 > v v5(ov,h) or v 1v25 > v 1v25(ov,h) v ss1 < v ss1(rst) and v ss2 < v ss2(rst) enb and enbat1 and enbat2 = 0 figure 20: overvoltage of vreg, synchronous buck, 3v3, or v5 with reset by en adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 33 figure 21: possible overvoltage cases for v5p npor set low due to any ov npor forces wd start low pok5v after t dfilt and v v5 < v v5(pok,l) case 1: v v5p(ov,h) < v v5p < v v5p(disc) and t > t dov t = t dov f osc f osc ov forces lx1 to stop switching v v5p(ov,h) v vbat v v5p(disc) lx1 1v25 3v3 v5 v5p npor wd start pok5v ss1 comp1 vreg lx2 ss2 comp2 ff0 ff1 ov forces lx2 to stop switching case 2: v v5p > v v5p(ov,h) but t < t dov v v5p(ov,h) v vbat v v5p(disc) t = t dov v v5p(ov,l) v5p npor wd start pok5v ff0 ff1 f osc f osc lx1 1v25 3v3 v5 ss1 comp1 vreg lx2 ss2 comp2 npor forces wd start low v v5p(ov,h) v vbat v v5p(disc) case 3: v v5p > v v5p(disc) v5p npor wd start pok5v ff0 ff1 f osc f osc lx1 1v25 3v3 v5 ss1 comp1 vreg lx2 ss2 comp2 npor after t dfilt and v v5p(sense) < v v5p(uv,lx) pok5v after t dfilt and v v5p(sense) < v v5p(pok,l) adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 34 figure 22: hiccup mode operation when vreg is shorted to gnd t hic1(ocp) v ss1(rst) lx1 ss1 comp1 en_hic1 ocp1 hic1 v ss1(offs) v ea(vo,max) , ocl 1 = 1 v pwm1(offs) ff0 ff1 npor vreg 1.3 v typ t dffx(uv) to detect hiccup mode, uv sensing must be delayed by t dffx(uv) uv of v5 or v5p vreg shorted to ground t hic1(ocp) t hic1(ocp) f osc f osc /4 f osc /8 adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 35 figure 23: hiccup mode operation when the synchronous buck output is shorted to gnd v ss2(rst) lx2 ss2 comp2 en_hic2 ocp2 hic2 v hic2(en) v ss2(offs) v pwm2(offs) ff0 ff1 npor 1v25/ fbadj 450 mv typ t dffx(uv) to detect hiccup mode, uv sensing must be delayed by t dffx(uv) synchronous buck output shorted to ground v ea2(vo,max) , ocl 2 =1 f osc f osc /4 f osc /8 t hic2(ocp) t hic2(ocp) t hic2(ocp) adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 36 npor latches ff0 and ff1 t > 24 ms t < 16 ms t wd(fault) npor wd start clk in wd fault t wd(to,slow) set to 20 ms ( 4m s) t < 16 ms t dwd(start) ff0 ff1 figure 24: typical watchdog timer operation wd will not indicate a fault if the rising edges of clk in occur within 16 ms of each other. wd will indicate a fault if the rising edges of clk in occur more than 24 ms apart. npor latches ff0 and ff1 t dwd(start) ? t dnpor(on) t wd(fault) t wd(fault) t wd(to,slow) t wd(fault) npor wd start clk in wd fault t wd(to,slow) startup t wd(to,slow) t dwd(start) t dwd(start) t dwd(start) t dwd(start) + t wd(to,slow) + t wd(fault) t dfilt + t dnpor(on) all regs_ok ff0 ff1 figure 25: watchdog timer operation showing start delay and missing clk in after startup, if clk in is stuck low (or high), npor will periodically pulse low for 2 ms. the time between npor fault indications will be t dwd(start) + t wd(to,slow) + t wd(fault) . adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 37 pwm switching frequency (r fset ) when the pwm switching frequency is chosen, the designer should be aware of the minimum controllable on-time, t on(min) , of the A4408. if the systems required on-time is less than the A4408 minimum controllable on-time, then switch node jitter will occur and the output voltage will have increased ripple or oscillations. the pwm switching frequency should be calculated using equa- tion 1, where t on(min) is the minimum controllable on-time of the A4408 (85 ns typ ) and v vin(max) is the maximum required operational input voltage (not the peak surge voltage). f osc < 5.35 v t v on(min) vin(max) (1) if the A4408 synchronization function is used, then the base oscillator frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency accord- ing to equation 1. charge pump capacitors the charge pump requires two capacitors: a 1 f connected from pin vcp to vin, and a 0.22 f connected between pins cp1 and cp2. these capacitors should be high-quality ceramic capacitors, such as x5r or x7r, with voltage ratings of at least 16 v. pre-regulator output inductor (l1) for peak current-mode control, it is well known that the system will become unstable when the duty cycle is above 50% without adequate slope compensation (s e ). however, the slope compen- sation in the A4408 is a fixed value based on the oscillator fre- quency (f osc ). therefore, its important to calculate an inductor value so the falling slope of the inductor current (s f ) will work well with the A4408 fixed slope compensation. equation 2 can be used to calculate a range of values for the output inductor for the pre-regulator. in equation 2, slope com- pensation (s e1 ) is a function of the switching frequency (f osc ) according to equation 3, and v f is the asynchronous diodes forward voltage. (2) (5.25 v+ v) f s e1 s e1 l1 (5.45 v+ v) f 2 (3) s= 7.18810 -4 f+ 0.0425 e1 osc when using equations 2 and 3, f osc is in khz, s e1 is in a/s, and l1 will be in h. if equation 2 yields an inductor value that is not a standard value, then the next highest standard value should be used. the final inductor value should allow for 10%-20% of initial tolerance and 20%-30% of inductor saturation. the inductor should not saturate given the peak operating cur- rent according to equation 4. in equation 4, v vin(max) is the maximum continuous input voltage, such as 18 v, and v f is the asynchronous diodes forward voltage. (4) s (5.25 v+ v) e1 f 1.1 f (v + v) os cv in(max) i= 5.1 a? peak1 f after an inductor is chosen, it should be tested during output short-circuit conditions. the inductor current should be moni- tored using a current probe. a good design should ensure the inductor or the regulator are not damaged when the output is shorted to ground at maximum continuous input voltage and the highest expected ambient temperature. the inductor ripple current can be calculated using equation 5. (5) (v ?5 .35 v) 5.35 v vin fl v osc1 vin i= l1 pre-regulator output capacitance the output capacitors filter the output voltage to provide an acceptable level of ripple voltage, and they store energy to help maintain voltage regulation during a load transient. the voltage rating of the output capacitors must support the output voltage with sufficient design margin. within the first few pwm cycles, the deviation of v vreg will depend mainly on the magnitude of the load step (i load1 ), the value of the output inductor (l1), the output capacitance (c out ), and the maximum duty cycle of the pre-regulator (d max1 ). equations 6 and 7 can be used to calculate a minimum output capacitance to maintain v vreg within 1% of its target for a 750 ma load step at only 6 v vin . (6) l1 (750 ma) 2 2 (6.0 v? 5.25 v) (0.01 5.25 v) d max1 c out(vreg) (7) d max = 1 f osc f osc ?80 ns () after the load transient occurs, the output voltage will deviate design and component selection adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 38 from its nominal value until the error amplifier can bring the output voltage back to its nominal value. the speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop bandwidth of the system. selection of the compensation components (r z1 , c z1 , c p1 ) are discussed in more detail in the pre-regulator compensation sec- tion of this datasheet. the output voltage ripple (v vreg ) is a function of the output capacitors parameters: c out , esr co , and esl co according to equation 8. (8) v= i esr+ vreg lc o v? v vin vreg l o esl+ co i l 8 f osco ut c the type of output capacitors will determine which terms of equation 8 are dominant. for the A4408 and automotive environ- ments, only ceramic capacitors are recommended. the esr co and esl co of ceramic capacitors are virtually zero, so the peak- to-peak output voltage ripple of v vreg will be dominated by the third term of equation 8. i l 8 f osc out c (9) v vreg(pp) = pre-regulator ceramic input capacitance the ceramic input capacitors must limit the voltage ripple at the vin pin to a relatively low voltage during maximum load. equa- tion 10 can be used to calculate the minimum input capacitance, i 0.25 vreg(max) 0.90 f oscp p 50 mv (10) c in where i vreg(max) is the maximum current from the pre-regulator, (11) i= i+ + vreg(max )v 5 v5p 3v3 ii + v out(adj) out(adj) i 5.25 v 80% + 20 ma a good design should consider the dc bias effect on a ceramic capacitoras the applied voltage approaches the rated value, the capacitance value decreases. the x7r-type capacitors should be the primary choices due to their stability versus both dc bias and temperature. for all ceramic capacitors, the dc bias effect is even more pronounced on smaller case sizes, so a good design will use the largest affordable case size (i.e. 1206/16 v or 1210/50 v). also, for improved emi/emc performance, it is recommended that two small capacitors be placed as close as physically possible to the vin pins to address frequencies above 10 mhz. for exam- ple, a 0.1 f/x7r/0603 and a 220 pf/cog/0402 capacitor will address frequencies up to 20 mhz and 200 mhz, respectively. pre-regulator asynchronous diode (d1) the highest peak current in the asynchronous diode (d1) occurs during overload and is limited by the A4408. equation 4 can be used to calculate this current. the highest average current in the asynchronous diode occurs when v vin is at its maximum, d boost = 0%, and d buck = mini- mum (10%), i avg = (1 C d buck ) i vreg(max) = 0.9 i vreg(max) (12) where i vreg(max) is calculated using equation 11. pre-regulator boost mosfet (q1) the maximum rms current in the boost mosfet (q1) occurs when v vin is very low and the boost operates at its maximum duty cycle, (13) i= q1(rms) d max(bst) iC peak1 i l1 i l1 2 2 + 12 ) ( [ ] where i peak1 and i l1 are derived using equations 4 and 5, respectively, and d max(bst) is identified in the electrical charac- teristics table. the boost mosfet should have a total gate charge of less than 14 nc at a v gs of 5 v. the v ds rating of the boost mosfet should be at least 20 v. several recommended part numbers are shown in the functional block diagram / typical schematic. pre-regulator boost diode (d2) in buck mode, the maximum average current in this diode is simply the output current, calculated with equation 11. however, in buck- boost mode, the peak currents in this diode may increase signifi- cantly. the A4408 will limit the current to the value calculated by equation 4. pre-regulator soft-start and hiccup timing (c ss1 ) the soft-start time of the pre-regulator is determined by the value of the capacitance at the soft-start pin (c ss1 ). if the A4408 is starting into a very heavy load, a very fast soft- start time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. this occurs because the total of the full load current, the inductor ripple current, and the additional cur- rent required to charge the output capacitors (i c(out) = c out v out / t ss ) is higher than the pulse-by-pulse current threshold, as shown in figure 26. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 39 i lim i load output capacitor current, i c(out) t ss } figure 26: output current (i co ) during startup to avoid prematurely triggering hiccup mode, the soft-start time (t ss1 ) should be calculated using equation 14, (14) t ss1 = 5.35 v c out i c(out) where c out is the output capacitance, and i c(out) is the amount of current allowed to charge the output capacitance during soft- start (recommend 0.1 a < i c(out) < 0.3 a). higher values of i c(out) result in faster soft-start time, and lower values of i c,out ensure that hiccup mode is not falsely triggered. allegro recom- mends starting the design with an i c,out of 0.1 a and increasing it only if the soft-start time is too slow. then, c ss1 can be calculated based on equation 15: (15) c ss1 i ss1(su) ss1 t 0.8 v if a non-standard capacitor value for c ss1 is calculated, the next higher value should be used. the voltage at the soft-start pin will start from 0 v and will be charged by the soft-start current (i ss1(su) ). however, pwm switching will not begin immediately because the voltage at the soft-start pin must rise above the soft-start offset voltage (v ss1(offs) ). the soft-start delay (t dss1 ) can be calculated using equation 16. (16) t dss1 ss1 = c v ss1(offs) i ss1(su) when the A4408 is in hiccup mode, the soft-start capacitor sets the hiccup period. during a startup attempt, the soft-start pin charges the soft-start capacitor with i ss1(su) and discharges the same capacitor with i ss1(hic) between startup attempts. pre-regulator compensation (r z1 , c z1 , c p1 ) although the A4408 can operate in buck-boost mode at low input voltages, it still can be considered a buck converter when examining the control loop. the following equations can be used to calculate the compensation components. first, select the target crossover frequency for the final system. while switching at over 2 mhz, the crossover is governed by the required phase margin. since a type ii compensation scheme is used, the system is limited to the amount of phase that can be added. hence, a crossover frequency (f c1 ) in the region of 35 khz is selected. the total system phase will drop off at crossover frequencies about 100 khz. the r z1 calculation is based on the gain required to set the crossover frequency and can be calculated by equation 17. (17) r z1 = 13.38 f c c1 out gm power1 ea1 gm the series capacitor (c z1 ) along with the resistor (r z1 ) set the location of the compensation zero. this zero should be placed no lower than ? of the crossover frequency and should be kept to minimum value. equation 18 can be used to estimate this capaci- tor value. (18) c z1 > 4 2 r f z1 c1 allegro recommends adding a small capacitor (c p1 ) in parallel with the series combination of r z1 /c z1 to roll off the error amps gain at high frequency. this capacitor usually helps reduce lx1 pulse-width jitter, but if too large, it will also decrease the loops phase margin. allegro recommends using this capacitor to set a pole at approxi- mately 5 the loops crossover frequency (f c1 ), as shown in equa- tion 19. if a non-standard capacitor value results, the next higher available value should be used. (19) c p1 1 2 r 5 f z1 c1 an excel-based design tool is available from allegro that accepts customer specifications and recommends values for both the power and compensation components. the pre-regulator bode plot in figure 27 was generated with this tool. the bandwidth of this system (f c1 ) is 30 khz, the phase margin (pm1) is 61 degrees, and the gain margin (gm1) is 25 db. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 40 figure 27: bode plot for the pre-regulator r z1 = 22.1 k, c z1 = 1.5 nf, c p1 = 47 pf lo = 4.7 h, co = 5 10 f/16 v/1206 synchronous buck component selection similar design methods can be used for the synchronous buck; however, the complexity of variable input voltage and boost operation are removed. setting the output voltage (r fb1 and r fb2 ) the A4408 was optimized to deliver 1.25 v from the synchro- nous buckwhere the output of the synchronous buck is con- nected directly to the fb 1v25/adj pin. the absence of a resistor divider from vout to the fb 1v25/adj pin results in robust fault conditions (i.e. if the feedback trace is open, the output of the synchronous buck will be 0 v). if required, the output of the synchronous buck may be pro- grammed from 1.25 to 3.3v . this is achieved by adding a resistor divider from its output to ground and connecting the center point to the fb 1v25/adj pin, as shown in figure 28. lx2 1v25/fb adj adj. sync. buck regula to r r fb2 r fb1 l2 v out(adj) A4408 figure 28: setting the synchronous buck output the ratio of the feedback resistors can be calculated based on equation 20. (20) = v out(adj) 1.25 v r fb1 r fb2 ?1 () synchronous buck output inductor (l2) equation 21 can be used to calculate a range of values for the out- put inductor for the synchronous buck regulator. slope compensa - tion (s e2 ) can be calculated using equation 22. (21 ) v out(adj) 2 s e2 l2 v out(adj) s e2 (22) s e2 osc = 3.06310 -4 f+ 0.0175 when working with equations 21 and 22, f osc is in khz, s e2 is in a/s, and l2 will be in h. if equation 21 yields an inductor value that is not a standard value, then the next closest available value should be used. the final inductor value should allow for 10%-20% of initial toler- ance and 20%-30% for inductor saturation. the inductor should not saturate given the peak current at over- load according to equation 23. (23) s v e2 out(adj) i= 2. 4a ? peak2 1.1 f osc 5.45 v once the inductor value is known, the ripple current can be calcu- lated using equation 24. (24) (5.35 v vv out(adj) out(adj) ) i= l2 f osc l2 5.35 v synchronous buck output capacitance within the first few pwm cycles, the deviation of v out(adj) will depend mainly on the magnitude of the load step (i load2 ), the value of the output inductor (l2), the output capacitance (c out(adj) ), and the maximum duty cycle of the synchronous converter (d max2 ). equations 25 and 26 can be used to calculate a minimum output capacitance to maintain 1.25 v within 1.2% of its target for a 400 ma load step. (25) l2 (400 ma) 2 2 v (0.012 1.25v) d out(adj) max2 c out(1v25) (26) d max2 = 1 f osc f osc ?1 10 ns () after the load transient occurs, the output voltage will deviate from its nominal value until the error amplifier can bring the output voltage back to its nominal value. the speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop bandwidth of the system. selection of the compensation components (r z2 , c z2 , c p2 ) are discussed in more detail in the synchronous buck compensation section of this datasheet. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 41 allegro recommends the use of ceramic capacitors for the syn- chronoous buck. the peak-to-peak voltage ripple of the synchro- nous buck (v out(adj,pp) ) can be calculated with equation 27. i l2 8 f osc out(adj) c (27) v vout(adj,pp) = synchronous buck compensation (r z2 , c z2 , c p2 ) again, similar techniques as used with the pre-regulator can be used to compensate the synchronous buck. for the synchronous buck, select 100 khz for the crossover fre- quency (f c2 ) of the synchronous buck. then, equation 28 can be used to calculate r z2 . v 2 f c out(adj) c2 out(adj) 1.25 v gm power2 ea2 gm (28) r z2 = the series capacitor (c z2 ) along with the resistor (r z2 ) set the location of the compensation zero. this zero should be placed no lower than ? of the crossover frequency and should be kept to minimum value. equation 29 can be used to estimate this capaci- tor value. 4 2 r f z2 c2 (29) c z2 > allegro recommends adding a small capacitor (c p2 ) in parallel with the series combination of r z2 /c z2 to roll off the error amp gain at high frequency. this capacitor usually helps reduce lx2 pulse-width jitter, but if too large, it will also decrease the loops phase margin. allegro recommends using this capacitor to set a pole at approxi- mately 8 the loops crossover frequency (f c2 ), as shown in equa- tion 30. if a non-standard capacitor value results, use the next higher available value. 1 2 r 8 f z2 c2 (30) c p2 allegros excel-based design tool accepts specifications for the synchronous buck and recommends values for both the power and compensation components. the synchronous buck bode plot in figure 29 was generated with this tool. the bandwidth of this system (f c2 ) is 90 khz, the phase margin (pm2) is 56 degrees, and the gain mar gin (gm2) is 17 db. -75 -60 -45 -30 -15 0 15 30 45 60 75 90 105 120 135 150 165 180 -60 -40 -20 0 20 40 60 80 100 1000 10000 100000 1000000 phase - gain - db frequency - hz synchronous buck bode plot gain phase figure 29: bode plot for the sync. buck at 1.25 v out r z2 = 6.81 k, c z2 = 1.5 nf, c p2 = 47 pf l2 = 4.7 h, c out(adj) = 3 10 f/16 v/1206 synchronous buck soft-start and hiccup timing the soft-start time of the synchronous buck is determined by the value of the capacitance at the soft-start pin (c ss2 ). if the A4408 is starting into a very heavy load, a very fast soft- start time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. to avoid prematurely triggering hiccup mode, the soft-start time (t ss2 ) should be calculated according to equation 31, c out(adj) i c(out) (31) t ss2 out(adj) = v where v out(adj) is the output voltage, c out(adj) is the output capacitance, i c(out) is the amount of current allowed to charge the output capacitance during soft-start (recommend 75 ma < i c(out) < 150 ma). higher values of i c(out) result in faster soft- start times and lower values of i c(out) ensure that hiccup mode is not falsely triggered. for the synchronous buck, allegro recom- mends starting the design with an i c(out) of 100 ma and increas- ing it only if the soft-start time is too slow. then, c ss2 can be selected based on equation 32, i ss2(su) ss2 t 800 mv (32) c ss2 > adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 42 if a non-standard capacitor value for c ss2 is calculated, the next larger value should be used. the voltage at the soft-start pin will start from 0 v and will be charged by the soft-start current (i ss2(su) ). however, pwm switch - ing will not begin instantly because the voltage at the soft-start pin must rise above the soft-start offset voltage (v ss2(offs) ). the soft- start delay (t dss2 ) can be calculated using equation 33, v ss2(offs) i ss2(su) (33) t= c dss2 ss2 > () when the A4408 is in hiccup mode, the soft-start capacitor sets the hiccup period. during a startup attempt, the soft-start pin charges the soft-start capacitor with i ss2(su) and discharges the same capacitor with i ss1(hic) between startup attempts. linear regulators the three linear regulators only require a single ceramic capacitor located near the A4408 to ensure stable operation. the range of acceptable values is shown in the electrical characteristics table. a 2.2 f capacitor per regulator is a good starting point. as the ldo outputs are routed throughout the pcb, it is recom- mended that a 0.1 f/0603 ceramic capacitor be placed as close as possible to each load point for local filtering and high-fre- quency noise reduction. also, since the v5p output may be used to power remote cir- cuitry, its load may include external wiring. the inductance of this wiring will cause lc-type ringing and negative spikes at the v5p pin if a fast short-to-ground occurs. it is recommended that a small schottky diode be placed close to the v5p pin to limit the negative voltages, as shown in the applications schematic. the mss1p5 (or equivalent) is a good choice. internal bias (v cc ) the internal bias voltage should be decoupled at the vcc pin using a 1 f ceramic capacitor. it is not recommended to use this pin as a source. signal pins (npor, pok5v, ff0, ff1) the A4408 has many signal-level pins. the npor, pok5v, ff0, and ff1 are open-drain outputs and require external pull-up resis- tors. allegro recommends sizing the external pull-up resistors so each pin will sink less than 2 ma when it is a logic low. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 43 after the ring frequency has been measured, the total capacitance at the lx node must be estimated. for the buck-boost pre- regulator, the lx1 pin (5 to 10 pf), the pcb (10 to 30 pf), and the asynchronous diode will all contribute to the capacitance. the asynchronous diode junction capacitance (~70 pf at 12 v r ) is usually shown in the datasheet, as shown in figure 32. for the synchronous buck, there is no external diode, so the total capacitance will consist of the lx2 pin, the internal synchronous mosfet (10 to 20 pf), and the pcb. figure 32: typical diode junction capacitance the total capacitance is calculated using equation 34, c tot = c diode + c lx1_pin + c pcb (34) = 70 pf + 7.5 pf + 20 pf = 97.5 pf knowing the ring frequency and the total capacitance, the induc- tive component of the ringing can be calculated using equation 35. 1 4 2 f ring 2 c tot (35) l ring = 1 4 2 192 mhz 2 97.5 pf l ring == 7.05 nh the snubber resistor is calculated using equation 36. (36) l ring c tot r snub = 7.05 nh 97.5 pf r snub = = 8.66 (standard value) finally, the snubber capacitor can be calculated using equa- tion 37. if equation 37 results in a non-standard value, use the next higher standard value. rc snubber calculations (r snubx , c snubx ) allegro strongly recommends including provisions for rc snubbers from lx1, lx2, and lxb to ground, as shown in the applications schematic. the lx1 and lx2 snubbers are required to meet automotive emc requirements. the lxb snubber may be needed to reduce system noise when v vin is less than 7 v and the boost mosfet (lg pin) starts switching. if the A4408 is used in buck-only mode, the lxb snubber is not necessary. a simple method to calculate the rc snubber component values is presented here. use the tip-and-barrel technique on a oscilloscope probe to mea- sure the frequency of the turn-on ringing of the lx node without an rc snubber. the oscilloscope bandwidth must be set to its maximum, at least 200 mhz. the tip-and-barrel oscilloscope probe technique is show in figure 30. typical lx ringing and frequency without a snubber are shown in figure 31. figure 30: measuring lx ringing with tip-and-barrel figure 31: typical lx1 ring frequency at turn-on without a snubber and v vin = 12 v: f ring = 192 mhz adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 44 figure 34 shows the lx waveform with the rc snubber compo- nents, 8.66 + 270 pfthe 192 mhz high-frequency ringing has been eliminated. figure 34: lx1 waveform including an rc snubber consisting of 8.66 + 270 pf 1 2.5 f ring r snub (37) c snub = 1 2.5 192 mhz 8.66 c snub == 270 pf (standard) it is very important to calculate the power dissipated by the resistor at the maximum steady-state (dc) input operating volt- age, using equation 38. once the maximum power dissipation is known, an adequate component considering power derating at the maximum ambient temperature can be chosen. in this example, v vin(max,dc) = 18 v and f osc = 2.2 mhz is used. p snub = ? c snub v vin 2 f sw (38) p snub = ? 270 pf 18 v 2 2.2 mhz = 96 mw t o support 100 mw at high ambient temperature, a 1206 size resistor is needed. a 1206 size resistor can dissipate 250 mw up to 100c and 100 mw (40%) up to almost 135c, as shown in figure 33. 0 10 20 30 40 50 60 70 80 90 100 110 25 35 45 55 65 75 85 95 105 115 125 135 145 155 165 power rating (%) ambient temperature (c) typical resistor power derating vs temperature figure 33: resistor power derating versus ambient temperature adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 45 pcb layout recommendations figure 35: charge pump capacitor c1 and c2. place these components near pins 1, 2, 37, and 38. figure 36: recommended placement and connection of the two charge pump capacitors. 1) start the layout by placing these components near pins 1, 2, 37, and 38. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 46 figure 37: the most critical power component connections for the pre-regulator. place these components onto the pcb layout after the charge pump capacitors. figure 38: recommended placement and routing of the most critical power components. 1) all of these components must be on the same layer as the A4408 (u1). 2) routing between these components must not be interrupted by other traces. 3) input capacitors (c34, c3, c4, c5, and c6) are located very close to the vin pins. 4) minimize the total loop area from c34/c6/c5 through u1 + d1. 5) the six ground vias north of c3 are placed so they only conduct dc current. 6) the switch node trace (lx1) is very short and just wide enough to carry about 3 a. 7) high frequency currents passing through d1 are directly routed to c34, c6, c5, and c4. 8) the snubber components connect directly from the lx1 node to ground. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 47 figure 39: vreg capacitors (c8-c14) and pgnd connections. the vreg capacitors are the input bypass capacitors for the synchronous buck. place these capacitors so the loop from the vreg to pgnd is short and uninterrupted. figure 40: recommended placement of the vreg capacitors and their pgnd connection. 1) place these components on the same layer as the A4408 (u1). 2) minimize the loop from capacitors c8-c12 to the vreg pin and pgnd pin. 3) the ground connection from the capacitors to the pgnd pins is uninterrupted. 4) connect the two pgnd pins to the thermal pad (i.e. ground) under the A4408. 5) note, the lx2 trace (pins 23 and 24) uses a via to avoid interrupting the pgnd trace. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 48 figure 41: recommended placement and routing of the boost mosfet and diode (q1, d2), local bypass capacitors (c33, c35), and snubber components (rn3, cn3). 1) minimize the hot loop between c33/c35 to d2 and to q2. 2) place a connection to the ground plane outside the hot loop (see 4 vias next to c35). 3) include a thermal area on the bottom of the pcb (blue polygon) as thermal relief for q1. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 49 figure 42: synchronous buck output capacitors (c16-c18), snubber (rn2, cn2), and feedback resistor divider (rfb1, rfb2). figure 43: recommended placement and routing of the synchronous buck inductor (l2), snubber (rn2, cn2), output capacitors (c16-c18), and feedback resistor divider (rfb1, rfb2). 1) minimize the length and width of the lx2 trace. the width should accommodate 2.4 a max . 2) the lx2 trace is on the bottom layer so the vreg capacitors can connect directly to pgnd. 3) the snubber is on the same layer as the inductor and is grounded at pgnd. 4) the feedback trace (1v25/fb adj ) is routed to the point of loading and after any filtering (b2). 5) if used, the feedback resistor divider (rfb1, rfb2) must be located near the fb adj pin. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 50 figure 44: ldo (v5p) output capacitor and negative clamp diode (c22, d5). figure 45: recommended placement and routing of the ldo (v5p), output capacitor (c22), and negative clamp diode (d5). 1) place the output capacitor and negative clamp diode close to the v5p output pin. 2) connect these two components to the ground plane near the A4408. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 51 figure 46: the comp1 (rz1, cz1, cp1) and comp2 (rz2, cz2, cp2) components. figure 47: recommended placement and routing of comp1 and comp2 components. 1) these components can by placed on the bottom of the pcb, near pins 9 and 20. 2) place a via very close to pins 9 and 20. 3) keep noisey traces, like lx1 and lx2, as far away as possible from these components. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 52 figure 48: the gate drive from lg (pin 33) to the boost mosfet. figure 49: recommended routing of the gate driver to the boost mosfet. 1) it is best to keep the gate drive trace (lg) short and on the same layer as u1 and q1 (i.e. no vias). 2) here, the trace routes on the top layer and makes a short vertical run under l1. 3) the return path for the gate driver is layer #2, which is a ground plane. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 53 package outline drawing for reference only ? not for tooling use (reference jedec mo-153 bdt-1) dimensions in millimeters not to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown a 1.10 max 0.90 0.05 0.15 0.00 0.27 0.17 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 38x 0.50 bsc 0.25 bsc 21 38 9.70 0.10 6.50 0.10 4.40 0.10 6.40 bsc gauge plane seating plane a b b exposed thermal pad (bottom surface) 3.00 0.10 branded face c 6.00 0.50 0.30 1.70 3.00 6.5 38 21 c pcb layout reference view terminal #1 mark area reference land pattern layout (reference ipc7351 sop50p640x120-39m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) figure 50 : package lv, 38-pin etssop adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 54 for the latest version of this document, visit our website: www.allegromicro.com revision history number date description C september 23, 2016 initial release 1 january 27, 2017 updated transconductance max value (page 8, 2nd condition), pulse-by-pulse current limit max value (page 9, 2nd condition), low-side mosfet leakage max value (page 10, 2nd condition), transconductance min and max values (page 10, 1st condition), high-side mosfet pulse-by-pulse current limit max value (page 11). deleted high-side mosfet pulse-by-pulse current limit 2nd condition (page 11). added footnote to boost duty cycle (lg pin) 1st condition (page 8) copyright ?2017, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. adjustable frequency buck or buck-boost pre-regulator with a synchronous buck, 3 internal ldos, watchdog timer, npor, and ff0/ff1 A4408 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com |
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